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| w w w .D at S Embedded Microprocessor a Product Features s s s s . U 80960CF-40, -33, -25 t4 32-Bit High-Performance Superscalar ee h Datasheet Socket and Object Code Compatible with 80960CA Two Instructions/Clock Sustained Execution Four 71 Mbytes/s DMA Channels with Data Chaining Demultiplexed 32-Bit Burst Bus with Pipelining s om c s s s w s s w 32-Bit Parallel Architecture -- Two Instructions/clock Execution -- Load/Store Architecture -- Sixteen 32-Bit Global Registers -- Sixteen 32-Bit Local Registers -- Manipulates 64-Bit Bit Fields -- 11 Addressing Modes -- Full Parallel Fault Model -- Supervisor Protection Model Fast Procedure Call/Return Model -- Full Procedure Call in 4 Clocks On-Chip Register Cache -- Caches Registers on Call/Ret -- Minimum of 6 Frames Provided -- Up to 15 Programmable Frames On-Chip Instruction Cache -- 4 Kbyte Two-Way Set Associative -- 128-Bit Path to Instruction Sequencer -- Cache-Lock Modes -- Cache-Off Mode High Bandwidth On-Chip Data RAM -- 1 Kbyte On-Chip Data RAM -- Sustains 128 bits per Clock Access Selectable Big or Little Endian Byte Ordering s w .D t a S a e h s s t e s Four On-Chip DMA Channels -- 71 Mbytes/s Fly-by Transfers -- 40 Mbytes/s Two-Cycle Transfers -- Data Chaining -- Data Packing/Unpacking -- Programmable Priority Method 32-Bit Demultiplexed Burst Bus -- 128-Bit Internal Data Paths to and from Registers -- Burst Bus for DRAM Interfacing -- Address Pipelining Option -- Fully Programmable Wait States -- Supports 8-, 16- or 32-Bit Bus Widths -- Supports Unaligned Accesses -- Supervisor Protection Pin High-Speed Interrupt Controller -- Up to 248 External Interrupts -- 32 Fully Programmable Priorities -- Multi-mode 8-Bit Interrupt Port -- Four Internal DMA Interrupts -- Separate, Non-maskable Interrupt Pin -- Context Switch in 625 ns Typical On-Chip Data Cache -- 1 Kbyte Direct-Mapped, Write Through -- 128 bits per Clock Access on Cache Hit U 4 .c m o w w w .D at Sh a et e 4U . om c Order Number: 272886-002 September 2002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960CF-40, -33, -25 32-Bit High-Performance Superscalar Embedded Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2002 AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 2 Datasheet Contents Contents 1.0 2.0 Purpose .......................................................................................................................................... 7 80960CF Processor Overview ...................................................................................................... 7 2.1 2.2 2.3 2.4 2.5 3.0 3.1 3.2 3.3 The 80960C-Series Core ...................................................................................................... 8 Pipelined, Burst Bus ............................................................................................................. 9 Instruction Set Summary ...................................................................................................... 9 Flexible DMA Controller ........................................................................................................9 Priority Interrupt Controller.................................................................................................... 9 Package Introduction ..........................................................................................................10 Pin Descriptions ..................................................................................................................11 80960CF Mechanical Data .................................................................................................16 3.3.1 80960CF PGA Pinout ............................................................................................16 3.3.2 80960CF PQFP Pinout (80960CF-33 and -25 Only) .............................................20 Package Thermal Specifications ........................................................................................22 Stepping Register Information ............................................................................................24 Sources for Accessories .....................................................................................................25 Absolute Maximum Ratings ................................................................................................26 Operating Conditions ..........................................................................................................26 Recommended Connections ..............................................................................................27 D.C. Specifications .............................................................................................................27 A.C. Specifications..............................................................................................................29 4.5.1 A.C. Test Conditions ..............................................................................................35 4.5.2 A.C. Timing Waveforms .........................................................................................36 4.5.3 Derating Curves .....................................................................................................40 Package Information ...................................................................................................................10 3.4 3.5 3.6 4.0 4.1 4.2 4.3 4.4 4.5 Electrical Specifications .............................................................................................................26 5.0 6.0 Reset, Backoff and Hold Acknowledge .....................................................................................41 Bus Waveforms ...........................................................................................................................43 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 80960CF Processor-Block Diagram ............................................................................................. 7 80960CF PGA Pinout--View from Top (Pins Facing Down) ......................................................16 80960CF PGA Pinout--View from Bottom (Pins Facing Up) .....................................................17 80960CF PQFP Pinout--Top View (80960CF-33 and -25 Only) ...............................................22 Measuring 80960CF PGA and PQFP Case Temperature..........................................................23 Register g0 .................................................................................................................................25 A.C. Test Load............................................................................................................................35 Input and Output Clocks Waveform............................................................................................36 CLKIN Waveform........................................................................................................................36 Output Delay and Float Waveform .............................................................................................37 Input Setup and Hold Waveform.................................................................................................37 NMI, XINT7:0 Input Setup and Hold Waveform..........................................................................38 Hold Acknowledge Timings ........................................................................................................38 Datasheet 3 Contents 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Bus Backoff (BOFF) Timings ...................................................................................................... 39 Relative Timings Waveforms ...................................................................................................... 39 Output Delay or Hold vs. Load Capacitance .............................................................................. 40 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC ................ 40 ICC vs. Frequency and Temperature--80960CF-33 and -25...................................................... 40 ICC vs. Frequency and Temperature--80960CF-40................................................................... 41 Cold Reset Waveform ................................................................................................................ 43 Warm Reset Waveform .............................................................................................................. 44 Entering the ONCE State ........................................................................................................... 45 Clock Synchronization in the 2-x Clock Mode ............................................................................ 46 Clock Synchronization in the 1-x Clock Mode ............................................................................ 46 Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 47 Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 48 Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 49 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 50 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 51 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus........................................ 52 Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus............................................. 53 Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 54 Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus .............................................. 55 Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 56 Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 57 Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 58 Burst, Pipelined Read Request With Wait States, 32-Bit Bus .................................................... 59 Burst, Pipelined Read Request With Wait States, 16-Bit Bus .................................................... 60 Burst, Pipelined Read Request With Wait States, 8-Bit Bus ...................................................... 61 Using External READY ............................................................................................................... 62 Terminating a Burst with BTERM ............................................................................................... 63 BOFF Functional Timing............................................................................................................. 64 HOLD Functional Timing ............................................................................................................ 65 DREQ and DACK Functional Timing .......................................................................................... 66 EOP Functional Timing............................................................................................................... 66 Terminal Count Functional Timing.............................................................................................. 67 FAIL Functional Timing............................................................................................................... 67 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................... 68 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ............................... 69 Idle Bus Operation ...................................................................................................................... 70 Tables 1 2 3 4 5 6 7 8 9 10 11 80960CF Instruction Set............................................................................................................. 10 Symbol Legend........................................................................................................................... 11 80960CF Pin Description--External Bus Signals ....................................................................... 12 80960CF Pin Description--Processor Control Signals .............................................................. 14 80960CF Pin Description--DMA and Interrupt Unit Control Signals .......................................... 15 80960CF PGA Pinout--In Signal Order ..................................................................................... 18 80960CF PGA Pinout--In Pin Order .......................................................................................... 19 80960CF PQFP Pinout--In Signal Order (80960CF-33 and -25 Only) ...................................... 20 80960CF PQFP Pinout--In Pin Order (80960CF-33 and -25 Only) ........................................... 21 Maximum TA at Various Airflows in oC (PGA Package Only) ..................................................... 23 80960CF PGA Package Thermal Characteristics ...................................................................... 24 4 Datasheet Contents 12 13 14 15 16 17 18 19 20 21 80960CF PQFP Package Thermal Characteristics ....................................................................24 Die Stepping Cross Reference ...................................................................................................25 Absolute Maximum Ratings ........................................................................................................26 Operating Conditions ..................................................................................................................26 D.C. Specifications .....................................................................................................................28 80960CF AC Characteristics (40 MHz) ......................................................................................29 80960CF AC Characteristics (33 MHz) ......................................................................................31 80960CF AC Characteristics (25 MHz) ......................................................................................33 Reset Conditions ........................................................................................................................42 Hold Acknowledge and Backoff Conditions ................................................................................42 Revision History Date September 2002 June 1996 Revision 002 001 Description References to the -16 MHz product have been removed from the datasheet. Initial release of the datasheet. Datasheet 5 Contents This page intentionally left blank. 6 Datasheet 80960-40, -33, -25 1.0 Purpose This document provides electrical characteristics of Intel's i960(R) CF embedded microprocessor. For functional descriptions consult the i960(R) CA/CF Microprocessor User's Manual (order number 270710). To obtain data sheet updates and errata, visit the Intel World Wide Web site at http://www.intel.com or contact your Intel field sales representative. 2.0 80960CF Processor Overview Intel's 80960CF is the second processor in the series of superscalar i960 microprocessors that also includes the 80960CA and the 80960HA/HD/HT. Upgrading from the 80960CA to the 80960CF is straightforward because the two processors are socket- and object code-compatible. As shown in Figure 1, the 80960CF's instruction cache is 4 Kbytes; data cache is 1 Kbyte (80960CA instruction cache is 1 Kbyte; it does not have a data cache.) This extra cache on the CF adds a significant performance boost over the CA. Figure 1. 80960CF Processor-Block Diagram Four-Channel Instruction Prefetch Queue Instruction Cache (4 Kbyte, Two-Way Set Associative) Interrupt Port 128-BIT CACHE BUS Programmable Interrupt Controller Multiply/Divide Unit Execution Unit Register-side Machine Bus Memory-side Machine Bus Parallel Instruction Scheduler DMA Controller Memory Region Configuration Bus Controller Bus Request Queues 1 Kbyte Direct Mapped Data Cache 1 Kbyte Data RAM 5 to 15 Sets Register Cache Address Data DMA Port Control Six-Port Register File 64-Bit SRC1 Bus 64-Bit SRC2 Bus 64-Bit DST Bus 32-Bit Base Bus 128-Bit Load Bus 128-Bit Store Bus Address Generation Unit F_CF001A Datasheet 7 80960-40, -33, -25 The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions per clock with peak execution of three instructions per clock. A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system's high-speed external memory subsystem. Also, the 80960CF's on-chip caching of instructions, procedure context and critical program data substantially decouples system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory subsystem. The 80960CF bus controller integrates full wait state and bus width control for highest system performance with minimal system design complexity. Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CF. The processor also integrates four complete data-chaining DMA channels and a high-speed interrupt controller on-chip. DMA channels perform single-cycle or two-cycle transfers, data packing and unpacking and data chaining. Block transfers -- in addition to source or destination synchronized transfers -- are supported. The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (latency) time of 625 ns. 2.1 The 80960C-Series Core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. This core may sustain execution of two instructions per clock (80 MIPS at 40 MHz). To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the C-Series core implementation. Factors that contribute to the core's performance include: * Parallel instruction decoding allows issuance of up to three instructions per clock. * Single-clock execution of most instructions * Parallel instruction decode allows sustained, simultaneous execution of two single-clock instructions every clock cycle. * * * * * * * Efficient instruction pipeline minimizes pipeline break losses. Register and resource scoreboarding allow simultaneous multi-clock instruction execution. Branch look-ahead and prediction allows many branches to execute with no pipeline break. Local Register Cache integrated on-chip caches Call/Return context. Two-way set associative, 4 Kbyte integrated instruction cache 1 Kbyte integrated Data RAM sustains a four-word (128-bit) access every clock cycle. Direct mapped, 1 Kbyte data cache, write through, write allocate 8 Datasheet 80960-40, -33, -25 2.2 Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CF to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at 40 MHz). Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Control Unit's main features include: * * * * * * * Demultiplexed, burst bus to exploit most efficient DRAM access modes Address pipelining to reduce memory cost while maintaining performance 32-, 16- and 8-bit modes for I/O interfacing ease Full internal wait state generation to reduce system cost Little and Big Endian support to ease application development Unaligned access support for code portability Three-deep request queue to decouple the bus from the core 2.3 Instruction Set Summary Table 1 summarizes the 80960CF instruction set by logical groupings. For a complete description of the instruction set, see the i960(R) CA/CF Microprocessor User's Manual (order number 270710). 2.4 Flexible DMA Controller A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to 71 Mbytes per second at 40 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CF core. 2.5 Priority Interrupt Controller A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller and a single non-maskable interrupt input. The 8-bit interrupt port may also be configured to provide individual interrupt sources that are level or edge triggered. 80960CF interrupts are prioritized and signaled within 225 ns of the request. When the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically completes in another 400 ns. The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications. Table 1 presents the 80960CF Instruction Set. Datasheet 9 80960-40, -33, -25 Table 1. 80960CF Instruction Set Data Movement Add Subtract Multiply Divide Load Store Move Load Address Remainder Modulo Shift *Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Processor Mgmt Flush Local Registers Modify Trace Controls Mark Force Mark Modify Arithmetic Controls Modify Process Controls *System Control *DMA Control NOTE: Instructions marked by (*) are 80960Cx extensions to the 80960 instruction set. Atomic Add Atomic Modify Unconditional Branch Conditional Branch Compare and Branch Branch Call Call Extended Call System Return Branch and Link Atomic Conditional Fault Synchronize Faults Call/Return Fault And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Arithmetic Logical Bit / Bit Field / Byte 3.0 3.1 Package Information Package Introduction This section describes the pins, pinouts and thermal characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package; the 80960CF-33 and -25 devices are also available in the 196-pin Plastic Quad Flat Package (PQFP). For complete package specifications and information, see the Intel Packaging Databook, available in individual chapters, at http://www.intel.com. 10 Datasheet 80960-40, -33, -25 3.2 Pin Descriptions This section defines the 80960CF pins. Table 2 presents the legend for interpreting the pin descriptions in Tables 3 through 5. Table 3 presents the external bus signals. Table 4 presents processor control signals. Table 5 presents the DMA and Interrupt Unit control signals. Note: All pins float while the processor is in the ONCE mode. Symbol Legend Symbol I O I/O - Input only pin Output only pin Pin may be either an input or output Pins "must be" connected as described Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation. Outputs are synchronous to PCLK2:1. S(E) Edge sensitive input S(L) Level sensitive input Asynchronous. Inputs may be asynchronous to PCLK2:1. A(E)Edge sensitive input A(L)Level sensitive input While the bus is in the Hold Acknowledge or Bus Backoff state, the pin: H(1) is driven to VCC H(0)is driven to VSS H(Z) floats H(Q)continues to be a valid input While the processor's RESET pin is low, the pin: R(1) is driven to VCC R(0)is driven to VSS R(Z) floats R(Q)continues to be a valid output Description Table 2. S(...) A(...) H(...) R(...) Datasheet 11 80960-40, -33, -25 Table 3. 80960CF Pin Description--External Bus Signals (Sheet 1 of 2) Name Type O S H(Z) R(Z) I/O S(L) H(Z) R(Z) Description ADDRESS BUS carries the physical address' upper 30 bits. A31 is the most significant bit; A2 is least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. Byte enable signals indicate the selected byte in each word. During burst accesses, A3:2 increment to indicate successive data cycles. DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit is carried on D0 and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. BYTE ENABLES select which of the four bytes addressed by A31:2 are active during an access to a memory region configured for a 32-bit data-bus width. BE3 applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0. 32-bit bus: BE3 BE2 BE1 BE0 Byte Enable 3 Byte Enable 2 Byte Enable 1 Byte Enable 0 enable D31:24 enable D23:16 enable D15:8 enable D7:0 A31:2 D31:0 BE3:0 O S H(Z) R(1) For accesses to a memory region configured for a 16-bit data-bus width, the processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively. 16-bit bus: BE3 BE2 BE1 BE0 Byte High Enable (BHE) enable D15:8 Not used (driven high or low) Address Bit 1 (A1) Byte Low Enable (BLE) enable D7:0 For accesses to a memory region configured for an 8-bit data-bus width, the processor uses the BE1 and BE0 pins as A1 and A0 respectively. 8-bit bus: BE3 BE2 BE1 BE0 O S H(Z) R(0) O S H(Z) R(1) Not used (driven high or low) Not used (driven high or low) Address Bit 1 (A1) Address Bit 0 (A0) W/R WRITE/READ is asserted for read requests and deasserted for write requests. The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire access in non-pipelined regions. In pipelined regions, W/R is not ensured to be valid in the last cycle of a read access. ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. READY is an input which signals the termination of a data transfer. READY is used to indicate that read data on the bus is valid or that a write-data transfer has completed. The READY signal works in conjunction with the internally programmed wait-state generator. When READY is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. When the READY pin is deasserted, wait states continue to be inserted until READY becomes asserted. This is true for the NRAD, NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended. BURST TERMINATE is an input which breaks up a burst access and causes another address cycle to occur. The BTERM signal works in conjunction with the internally programmed wait-state generator. When READY and BTERM are enabled in a region, the BTERM pin is sampled after the programmed number of wait states has expired. When BTERM is asserted, a new ADS signal is generated and the access is completed. The READY input is ignored when BTERM is asserted. BTERM must be externally synchronized to satisfy BTERM setup and hold times. WAIT indicates internal wait state generator status. WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs. WAIT may be used to derive a write-data strobe. WAIT may also be thought of as a READY output that the processor provides when it is inserting wait states. ADS READY I S(L) H(Z) R(Z) BTERM I S(L) H(Z) R(Z) WAIT O S H(Z) R(1) 12 Datasheet 80960-40, -33, -25 Table 3. 80960CF Pin Description--External Bus Signals (Sheet 2 of 2) Name Type O S H(Z) R(0) O S H(Z) R(0) O S H(Z) R(1) Description BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access. When the READY or BTERM input is used to extend wait states, the BLAST signal remains asserted until READY or BTERM terminates the access. DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in conjunction with DEN to provide control for data transceivers attached to the external bus. When DT/R is asserted, the signal indicates that the processor receives data. Conversely, when deasserted, the processor sends data. DT/R changes only while DEN is high. DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. DEN is used in conjunction with DT/R to provide control for data transceivers attached to the external bus. DEN remains asserted for sequential reads from pipelined memory regions. DEN is deasserted when DT/R changes. BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. LOCK is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation. To allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when LOCK is asserted. The processor performs DMA transfers while LOCK is active. HOLD REQUEST signals that an external agent requests access to the external bus. The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. BUS BACKOFF, when asserted, suspends the current access and causes the bus pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle and the access is resumed. HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus. When HOLDA is asserted, the external address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents. Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted, the state of the HOLDA pin is independent of the RESET pin. BUS REQUEST is asserted when the bus controller has a request pending. BREQ may be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor. BLAST DT/R DEN LOCK O S H(Z) R(1) HOLD I S(L) H(Z) R(Z) I S(L) H(Z) R(Z) BOFF HOLDA O S H(1) R(Q) BREQ O S H(Q) R(0) O S H(Z) R(Z) O S H(Z) R(Z) O S H(Z) R(Z) D/C DATA OR CODE is asserted for a data request and deasserted for instruction requests. D/C has the same timing as W/R. DMA DMA ACCESS indicates whether the bus request was initiated by the DMA controller. DMA is asserted for any DMA request. DMA is deasserted for all other requests. SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode. SUP is asserted when the request has supervisor privileges and is deasserted otherwise. SUP may be used to isolate supervisor code and data structures from nonsupervisor requests. SUP Datasheet 13 80960-40, -33, -25 Table 4. 80960CF Pin Description--Processor Control Signals (Sheet 1 of 2) Name Type Description RESET causes the chip to reset. When RESET is asserted, all external signals return to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles before being deasserted to ensure correct processor initialization. When the 1-x clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles before being deasserted to ensure correct processor initialization. The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin. The Hold Acknowledge bus state functions while the chip is reset. When the bus is in the Hold Acknowledge state when RESET is asserted, the processor internally resets, but maintains the Hold Acknowledge state on external pins until the Hold request is removed. When a Hold request is made while the processor is in the reset state, the processor bus grants HOLDA and enters the Hold Acknowledge state. RESET I A(L) H(Z) R(Z) FAIL O S H(Q) R(0) FAIL indicates failure of the self-test performed at initialization. When RESET is deasserted and initialization begins, the FAIL pin is asserted. An internal self-test is performed as part of the initialization process. When this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The FAIL pin is reasserted while the processor performs an external bus self-confidence test. When this self-test passes, the processor deasserts the FAIL pin and branches to the user's initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAIL pin may be disabled with the STEST pin. SELF TEST enables or disables the internal self-test feature at initialization. STEST is read on the rising edge of RESET. When asserted, internal self-test and external bus confidence tests are performed during processor initialization. When deasserted, only the bus confidence tests are performed during initialization. ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE is continuously sampled while RESET is low and is latched on the rising edge of RESET. To place the processor in the ONCE state: (1) Assert RESET and ONCE (order does not matter) (2) Wait for at least 16 CLKIN periods in 2-x mode--or 10,000 CLKIN periods in 1-x mode--after VCC and CLKIN are within operating specifications STEST I S(L) H(Z) R(Z) ONCE I A(L) H(Z) R(Z) (3) Deassert RESET (4) Wait at least 32 CLKIN periods (The processor may now be latched in the ONCE state while RESET is high.) To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert RESET and bring ONCE high prior to deasserting RESET. CLKIN must operate within the specified operating conditions until Step 4 completes. CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current. ONCE may be used by emulator products or board testers to effectively make an installed processor transparent in the board. CLKIN I A(E) H(Z) R(Z) I A(L) H(Z) R(Z) CLOCK INPUT is an input for the external clock needed to run the processor. The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2:1. CLOCK MODE selects the division factor applied to the external clock input (CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the processor's internal clock. When CLKMODE is low, CLKIN is divided by two to create PCLK2:1 and the processor's internal clock. CLKMODE should be tied high or low in a system as the clock mode is not latched by the processor. When left unconnected, the processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode. CLKMODE 14 Datasheet 80960-40, -33, -25 Table 4. 80960CF Pin Description--Processor Control Signals (Sheet 2 of 2) Name Type O S H(Q) R(Q) - - - - Description PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and outputs. All input and output timings are specified in relation to PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexibility in the system's allocation of capacitive loading on the clock. PCLK2:1 may also be connected at the processor to form a single clock signal. GROUND connections must be connected externally to a VSS board plane. POWER connections must be connected externally to a VCC board plane. VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode. Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments. Otherwise, VCCPLL should be connected to VCC. NO CONNECT pins must not be connected in a system. PCLK2:1 VSS VCC VCCPLL NC Table 5. 80960CF Pin Description--DMA and Interrupt Unit Control Signals Name Type I A(L) H(Z) R(Z) O S H(1) R(1) Description DMA REQUEST is used to request a DMA transfer. Each of the four signals requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests channel 1, etc. When two or more channels are requested simultaneously, the channel with the highest priority is serviced first. Channel priority mode is programmable. DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the four signals acknowledges a transfer for a single channel. DACK0 acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the requesting device of a DMA is accessed. END OF PROCESS/TERMINAL COUNT may be programmed as either an input (EOP3:0) or output (TC3:0), but not both. Each pin is individually programmable. When programmed as an input, EOPx causes termination of a current DMA transfer for the channel that corresponds to the EOPx pin. EOP0 corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured for source and destination chaining, the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. EOP3:0 are asynchronous inputs. When programmed as an output, the channel's TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated. TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer. When the last bus request is executed as multiple bus accesses, TCx stays asserted for the entire bus request. EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins may be configured in three modes: Dedicated Mode: Each pin is a dedicated external interrupt source. Dedicated inputs may be individually programmed to be level (low) or edge (falling) activated. XINT7:0 I A(E/L) H(Z) R(Z) Expanded Mode: The eight pins act together as an 8-bit vectored interrupt source. The interrupt pins in this mode are level activated. Since the interrupt pins are active low, the vector number requested is the 1's complement of the positive logic value place on the port. This eliminates glue logic to interface to combinational priority encoders which output negative logic. Mixed Mode: XINT7:5 are dedicated sources and XINT4:0 act as the five most significant bits of an expanded mode vector. The least significant bits are set to 010 internally. I A(E) H(Z) R(Z) NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated source. DREQ3:0 DACK3:0 EOP/TC3:0 I/O A(L) H(Z/Q) R(Z) NMI Datasheet 15 80960-40, -33, -25 3.3 3.3.1 80960CF Mechanical Data 80960CF PGA Pinout Figure 2 shows the complete 80960CF PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960CF PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). Table 6 presents the 80960CF pin names and package location in signal order. Table 7 presents the pin names and package location in pin order. See Section 4.0, "Electrical Specifications" on page 26 for specifications and recommended connections. Figure 2. 80960CF PGA Pinout--View from Top (Pins Facing Down) S R Q P N M L K J H G F E D C B A 1 2 3 4 5 6 D25 D29 D24 D27 D21 D23 D26 D19 D20 D22 D17 D18 VCC D16 VCC VSS D15 D14 VSS D13 VCC VSS D12 VCC VSS D11 D10 VSS D9 VCC VSS D8 D6 VCC D7 D4 D0 D5 D2 NC D3 D1 ONCE NC BOFF STEST NC NC NC FAIL NC NC 1 2 3 4 5 READY D31 HOLDA BTERM D28 BE3 HOLD D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 A21 A20 A19 VCC A16 VSS VCC VSS A13 VSS VCC VSS VCC VSS VCC VSS A7 VSS VCC VCC A4 NC DREQ0 NC 6 7 BE2 7 BE1 8 BLAST 9 DEN 10 W/R 11 DT/R 12 13 14 15 16 17 A25 S WAIT D/C LOCK A31 A27 ADS VCC VCC VCC DREQ2 DREQ1 VSS VSS VSS VSS VSS VSS VCC DREQ3 8 DACK0 DACK1 9 VCC DACK2 10 11 12 13 14 CLKMODE PCLK1 EOP/TC3 NMI A2 XINT4 XINT0 XINT1 15 16 17 BE0 VCC VCC DMA BREQ A29 A26 A23 VCCPLL DACK3 VCC EOP/TC0 VCC EOP/TC1 CLKIN PCLK2 EOP/TC2 XINT6 XINT3 RESET A22 R A18 Q A17 P A15 N A14 M A12 L A11 K A10 J A9 H A8 G A6 F A5 E A3 D XINT7 XINT5 C B XINT2 A F_CA002A 16 Datasheet 80960-40, -33, -25 Figure 3. 80960CF PGA Pinout--View from Bottom (Pins Facing Up) A B C D E F G H J K L M N P Q R S 1 NC 2 FAIL 3 NC 4 NC 5 NC 6 DREQ1 DREQ2 7 DREQ3 8 DACK1 DACK0 9 DACK2 10 DACK3 VCCPLL 11 EOP/TC0 12 EOP/TC1 13 EOP/TC2 PCLK2 CLKIN 14 EOP/TC3 PCLK1 CLK MODE 15 XINT1 16 RESET 17 XINT2 A XINT5 XINT7 B C A3 D A5 E A6 F A8 G A9 H A10 J A11 K A12 L A14 M A15 N A17 P A18 Q A22 R A25 S XINT3 XINT6 A2 A4 VCC A7 VCC VCC VCC A13 VCC A16 A19 A21 A23 A27 XINT0 XINT4 NMI VCC VSS VSS VSS VSS VSS VSS VSS VCC A20 A24 A26 A31 A28 A29 LOCK A30 BREQ D/C VCC VSS SUP DMA WAIT VCC VSS VSS VCC DT/R VSS VSS VCC W/R VCC VSS VSS BE0 DEN VSS VCC VSS VSS VSS VCC VCC BE1 VCC VCC ADS BE2 DREQ0 NC D30 HOLD BE3 NC NC D28 BTERM HOLDA NC ONCE NC D0 VCC VSS VSS VSS VSS VSS VSS VCC D22 D26 D31 READY STEST D1 D2 D4 D6 VCC D10 VCC VCC D14 VCC D18 D20 D23 D27 D29 BOFF D3 D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25 1 2 3 4 5 6 7 8 Metal Lid BLAST 9 10 11 12 13 14 15 16 17 F_CA003A Datasheet 17 80960-40, -33, -25 Table 6. 80960CF PGA Pinout--In Signal Order Address Bus Signal A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin S15 Q13 R14 Q14 S16 R15 S17 Q15 R16 R17 Q16 P15 P16 Q17 P17 N16 N17 M17 L16 L17 K17 J17 H17 G17 G16 F17 E17 E16 D17 D16 Data Bus Signal D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pin R3 Q5 S2 Q4 R2 Q3 S1 R1 Q2 P3 Q1 P2 P1 N2 N1 M1 L1 L2 K1 J1 H1 H2 G1 F1 E1 F2 D1 E2 C1 D2 C2 E3 BOFF B1 D/C DMA SUP S13 R12 Q12 VCCPLL B10 HOLD HOLDA BREQ R5 S4 R13 VCC Location B7, B9, B11, B12, C6, E15, F3, F16, G2, H16, J2, J16, K2, K16, M2, M16, N3, N15, Q6, R7, R8, R10, R11 Bus Control Signal BE3 BE2 BE1 BE0 Pin S5 S6 S7 R9 Processor Control Signal RESET Pin A16 I/O Signal DREQ3 DREQ2 Pin A7 B6 A6 B5 FAIL A2 DREQ1 DREQ0 STEST W/R S10 ONCE ADS R6 CLKIN READY BTERM S3 R4 CLKMODE PLCK1 PLCK2 WAIT BLAST S12 S8 VSS Location DT/R DEN S11 S9 B2 DACK3 C3 DACK2 DACK1 C13 C14 B14 B13 EOP/TC3 EOP/TC2 EOP/TC1 EOP/TC0 A14 A13 A12 A11 DACK0 A10 A9 A8 B8 LOCK S14 C7, C8, C9, C10, C11, C12, F15, G3, G15, H3, H15, J3, J15, K3, K15, L3, L15, M3, M15, Q7, Q8, Q9, Q10, Q11 XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 C17 C16 B17 C15 B16 A17 A15 B15 NMI D15 No Connect Location A1, A3, A4, A5, B3, B4, C4, C5, D3 18 Datasheet 80960-40, -33, -25 Table 7. 80960CF PGA Pinout--In Pin Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 Signal NC FAIL NC NC NC DREQ1 DREQ3 DACK1 DACK2 DACK3 EOP/TC0 EOP/TC1 EOP/TC2 EOP/TC3 XINT1 RESET XINT2 BOFF STEST NC NC DREQ0 DREQ2 VCC DACK0 VCC VCCPLL VCC VCC PCLK2 PCLK1 XINT0 XINT3 XINT5 Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 Signal D3 D1 ONCE NC NC VCC VSS VSS VSS VSS VSS VSS CLKIN CLKMODE XINT4 XINT6 XINT7 D5 D2 NC NMI A2 A3 D7 D4 D0 VCC A4 A5 D8 D6 VCC VSS VCC Pin F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 Signal A6 D9 VCC VSS VSS A7 A8 D11 D10 VSS VSS VCC A9 D12 VCC VSS VSS VCC A10 D13 VCC VSS VSS VCC A11 D15 D14 VSS VSS A13 A12 D16 VCC VSS Pin M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 Signal VSS VCC A14 D17 D18 VCC VCC A16 A15 D19 D20 D22 A20 A19 A17 D21 D23 D26 D28 D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 A21 A18 D24 D27 Pin R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Signal D31 BTERM HOLD ADS VCC VCC BE0 VCC VCC DMA BREQ A29 A26 A23 A22 D25 D29 READY HOLDA BE3 BE2 BE1 BLAST DEN W/R DT/R WAIT D/C LOCK A31 A27 A25 Datasheet 19 80960-40, -33, -25 3.3.2 80960CF PQFP Pinout (80960CF-33 and -25 Only) Table 8 and Table 9 present the 80960CF pin names with package location. Figure 4 shows the 80960CF PQFP pinout as viewed from the top side. See Section 4.0, "Electrical Specifications" on page 26 for specifications and recommended connections. Table 8. 80960CF PQFP Pinout--In Signal Order (80960CF-33 and -25 Only) Address Bus Signal A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Pin 153 152 151 145 144 143 142 141 139 138 137 136 134 133 132 130 129 128 124 123 122 120 119 118 117 116 114 113 112 111 Data Bus Signal D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pin 186 187 188 189 191 192 194 195 3 4 5 6 8 9 10 11 13 14 15 17 18 19 21 22 23 25 26 27 33 34 35 36 BOFF Bus Control Signal BE3 BE2 BE1 BE0 Pin 176 175 172 170 Processor Control Signal RESET FAIL STEST ONCE CLKIN Pin 91 45 46 43 87 85 74 78 Signal I/O Pin 60 59 58 57 DREQ3 DREQ2 DREQ1 DREQ0 W/R 164 CLKMOD E PCLK2 DACK3 DACK2 DACK1 DACK0 65 64 63 62 ADS 178 PCLK1 VSS READY BTERM 182 184 Location 2, 7, 16, 24, 30, 38, 39, 49, 56, 70, 75, 77, 81, 83, 88, 89, 92, 98, 105, 109, 110, 121, 125, 131, 135, 147, 150, 161, 165, 173, 174, 185, 196 EOP/TC3 EOP/TC2 EOP/TC1 EOP/TC0 69 68 67 66 WAIT BLAST 162 169 DT/R DEN 163 167 VCC Location XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 VCCPLL 72 NMI 107 106 102 101 100 95 94 93 LOCK 156 HOLD HOLDA BREQ 181 179 155 1, 12, 20, 28, 32, 37, 44, 50, 61, 71, 79, 82, 96, 99, 103, 115, 127, 140, 148, 154, 168, 171, 180, 190 D/C DMA SUP 159 160 158 No Connect Location 29, 31, 41, 42, 47, 48, 51, 52, 53, 54, 55, 73, 76, 80, 84, 86, 90, 97, 104, 126, 146, 149, 157, 166, 177, 183, 193 108 40 20 Datasheet 80960-40, -33, -25 Table 9. 80960CF PQFP Pinout--In Pin Order (80960CF-33 and -25 Only) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal VCC VSS D23 D22 D21 D20 VSS D19 D18 D17 D16 VCC D15 D14 D13 VSS D12 D11 D10 VCC D9 D8 D7 VSS D6 D5 D4 VCC NC VSS NC VCC D3 Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal D2 D1 D0 VCC VSS VSS BOFF NC NC ONCE VCC Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal EOP/TC1 EOP/TC2 EOP/TC3 VSS VCC VCCPLL NC PCLK2 VSS NC VSS PCLK1 VCC NC VSS VCC VSS NC CLKMODE NC CLKIN VSS VSS Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Signal XINT3 XINT4 XINT5 VCC NC VSS XINT6 XINT7 NMI VSS VSS A2 A3 A4 A5 VCC A6 A7 A8 A9 A10 VSS Pin 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Signal A18 A19 VSS A20 A21 A22 A23 VCC A24 A25 A26 A27 A28 NC VSS VCC NC VSS A29 A30 A31 VCC BREQ Pin 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 Signal NC DEN VCC BLAST BE0 VCC BE1 VSS VSS BE2 BE3 NC ADS HOLDA VCC HOLD READY NC BTERM VSS D31 D30 D29 D28 VCC D27 D26 NC D25 D24 VSS FAIL STEST NC NC VSS VCC NC NC NC NC NC VSS DREQ0 DREQ1 DREQ2 DREQ3 VCC DACK0 DACK1 DACK2 DACK3 EOP/TC0 A11 A12 A13 VSS NC VCC NC RESET VSS XINT0 XINT1 XINT2 VCC NC VSS VCC LOCK NC SUP D/C DMA VSS WAIT DT/R W/R A14 A15 A16 VSS A17 VSS Datasheet 21 80960-40, -33, -25 Figure 4. 80960CF PQFP Pinout--Top View (80960CF-33 and -25 Only) 98 50 99 49 147 Pin 1 148 196 F_CA004A 3.4 Package Thermal Specifications The 80960CF is specified for operation when case temperature (TC) is within the range of 0 C-100 C for 33 and 25 MHz, and 0 C-85 C for 40 MHz. TC may be measured in any environment to determine whether the 80960CF is within specified operating range. Case temperature should be measured at the center of the top surface, opposite the pins. Refer to Figure 5 for more information. Ambient temperature (TA) is calculated from thermal resistance from case to ambient (CA) using Equation 1: Equation 1. Calculation of Ambient Temperature (TA) T A = T C - ( P CA ) Table 10 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK). Note that TA is greatly improved by attaching fins or a heatsink to the package. Maximum power consumption (P) is calculated by using the typical ICC as tabulated in Section 4.4, "D.C. Specifications" on page 27 and VCC of 5 V. 22 Datasheet 80960-40, -33, -25 Figure 5. Measuring 80960CF PGA and PQFP Case Temperature Measure PGA temperature at center of top surface Measure PQFP case temperature at center of top surface. 168 - Pin PGA Pin 196 Pin 1 Table 10. Maximum TA at Various Airflows in oC (PGA Package Only) Airflow-ft/min (m/sec) fPCLK (MHz) 40 TA with Heatsink () 33 25 16 40 TA without Heatsink () 33 25 16 0 (0) 20 38 50 63 0 18 34 51 200 (1.01) 40 57 65 74 15 33 46 60 400 (2.03) 58 74 79 84 30 47 57 68 600 (3.04) 60 76 81 86 40 57 65 74 800 (4.06) 66 81 85 89 50 66 72 80 1000 (5.07) 68 84 87 90 52 67 74 81 0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Datasheet 23 80960-40, -33, -25 Table 11. 80960CF PGA Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 1.5 200 (1.01) 1.5 400 (2.03) 1.5 600 (3.07) 1.5 800 (4.06) 1.5 1000 (5.07) 1.5 JA JC Junction-to-Case (Case measured as shown in Figure 5.) Case-to-Ambient (No Heatsink) Case-to-Ambient (With Heatsink) 17 14 11 9 7.1 6.6 13 9 5.5 5 3.9 3.4 (See Note 3.) NOTES: 1. This table applies to 80960CF PGA plugged into socket or soldered directly to board. 2. JA = JC + CA 3. 0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 12. 80960CF PQFP Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 5 19 50 (0.25) 5 18 100 (0.50) 5 17 200 (1.01) 5 15 400 (2.03) 5 12 600 (3.04) 5 10 800 (4.06) 5 9 Junction-to-Case (Case Measured as shown in Figure 5.) Case-to-Ambient (No Heatsink) NOTES: 1. This table applies to 80960CF PQFP soldered directly to board. 2. JA = JC + CA JC 3.5 Stepping Register Information Upon reset, register g0 contains die stepping information (see Figure 6). The most significant byte contains ASCII 0; the upper middle byte contains an ASCII C; the lower middle byte contains an ASCII F. The least significant byte contains the stepping number in ASCII, and g0 retains this information until it is overwritten by the user program. Table 13 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. 24 Datasheet 80960-40, -33, -25 Figure 6. Register g0 ASCII DECIMAL 00 0 MSB 43 C 46 Stepping Number F Stepping Number LSB Table 13. Die Stepping Cross Reference g0 Least Significant Byte 01 02 03 04 05 Die Stepping A B C D E 3.6 Sources for Accessories The following is a list of suggested sources for 80960CF accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets 1. 3M Textool Test and Interconnection Products 6801 River Place Blvd. Mail Stop 130-3N-29 Austin, TX 78726-9000 (800) 328-0411 2. Augat, Inc. Interconnection Products Group 452 John Dietsch Blvd. Attleboro Falls, MA 02763 (508) 699-7646 3. Concept Mfg., Inc. (Decoupling Sockets) 400 Walnut St. Suite 609 Redwood City, CA 94063 (415) 365-1162 FAX: (415)265-1164 Heatsinks/Fins 1. Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234 (214) 243-4321 FAX: (214) 241-4656 2. Wakefield Engineering 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 Datasheet 25 80960-40, -33, -25 4.0 4.1 Electrical Specifications Absolute Maximum Ratings Table 14 presents the absolute maximum ratings for the 80960CF. Table 14. Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage wrt. VSS Voltage on Other Pins wrt. VSS Maximum Rating -65 C to +150 C -65 C to +110 C -0.5 V to + 6.5 V -0.5 V to VCC + 0.5 V Note: The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Warning: 4.2 Operating Conditions Table 15 presents the operating conditions for the 80960CF. Table 15. Operating Conditions Symbol Supply Voltage VCC 80960CF-40 80960CF-33 80960CF-25 Input Clock Frequency (2-x Mode) fCLK2x 80960CF-40 80960CF-33 80960CF-25 Input Clock Frequency (1-x Mode) fCLK1x 80960CF-40 80960CF-33 80960CF-25 Case Temp Under Bias TC PGA Pkg. (80960CF-40) PGA Pkg. (80960CF-33, -25 Only) 196-Pin PQFP (80960CF-33, -25 Only) 0 0 0 85 100 100 o Parameter Min Max Units Notes 4.75 4.50 4.50 0 0 0 8 8 8 5.25 5.50 5.50 80 66 50 40 33 25 V MHz MHz () C When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the processor is in a reset condition. When CLKIN is stopped, the specified RESET low time must be provided once CLKIN restarts and has stabilized. 26 Datasheet 80960-40, -33, -25 4.3 Recommended Connections Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960CF-based circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every VCC pin must be connected to the power plane, and every VSS pin must be connected to the ground plane. Pins identified as `NC' must not be connected in the system. Liberal decoupling capacitance should be placed near the 80960CF. The processor may cause transient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance may be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages may offer the lowest possible inductance. For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT, NMI), DMA (DREQ), or BTERM input should be connected to VCC through a pull-up resistor. Pull-up resistors should be in the in the range of 20 KW for each pin tied high. When READY or HOLD are not used, the unused input should be connected to ground. N.C. pins must always remain unconnected. For additional information refer to the i960(R) CA/CF Microprocessor User's Manual (order number 270710). 4.4 D.C. Specifications Table 16 presents the D.C. specifications of the 80960CF. Datasheet 27 80960-40, -33, -25 Table 16. D.C. Specifications Symbol VIL VIH VOL VOH VILR VIHR ILI1 Parameter (1) Input Low Voltage for all pins except RESET Input High Voltage for all pins except RESET Output Low Voltage Output High Voltage IOH = -1 mA IOH = - 200 A Min - 0.3 2.0 Max +0.8 VCC + 0.3 0.45 Units V V V V V Notes IOL = 5 mA 2.4 VCC - 0.5 - 0.3 3.5 1.5 VCC + 0.3 Input Low Voltage for RESET Input High Voltage for RESET Input Leakage Current for each pin except: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY, HOLD, CLKMODE Input Leakage Current for: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF Input Leakage Current for: READY, HOLD, CLKMODE Output Leakage Current Supply Current (80960CF-40, 33): ICC Max ICCTyp Supply Current (80960CF-25): ICC Max ICCTyp Supply Current (80960CF-16): ICC Max ICCTyp ONCE-mode Supply Current 80960CF-40 80960CF-33, -25, -16 V V 15 A 0 VIN VCC (2) ILI2 ILI3 ILO ICC 0 0 - 300 500 15 A A A VIN = 0.45 V (3) VIN = 2.4 V (4, 8) 0.45 VOUT VCC (5) (6) (5) (6) (5) (6) 1150 1000 950 775 750 575 225 150 0 12 12 12 mA mA mA mA mA ICC ICC IONCE mA CIN COUT CI/O Input Capacitance for: CLKIN, RESET, ONCE, READY, HOLD, DREQ3:0, BOFF, XINT7:0, NMI, BTERM, CLKMODE Output Capacitance of each output pin I/O Pin Capacitance pF pF pF FC = 1 MHz FC = 1 MHz (7) FC = 1 MHz NOTES: 1. 80960CF-33 and -25 under the conditions described in Section 4.2, "Operating Conditions" on page 26. 2. No pullup or pulldown. 3. These pins have internal pullup resistors. 4. These pins have internal pulldown resistors. 5. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Section 4.5.1, "A.C. Test Conditions" on page 35. 6. ICC Typical is not tested. 7. Output Capacitance is the capacitive load of a floating output. 8. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted. 28 Datasheet 80960-40, -33, -25 4.5 A.C. Specifications Table 17. 80960CF AC Characteristics (40 MHz) (Sheet 1 of 2) Symbol Parameter (1) Input Clock (2, 10) TF TC TCS TCH TCL TCR TCF CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time Output Clocks (2, 9) TCP T TPH TPL TPR TPF CLKIN to PCLK2:1 Delay PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time PCLK2:1 Fall Time Synchronous Outputs (9) Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 Output Float for all outputs Synchronous Inputs (2, 10, 11) Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 3 15 7 5 ns ns ns ns (7, 11) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 14 16 16 16 16 16 16 16 16 16 16 T/2 + 14 14 16 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) (T/2) - 2 (T/2) - 2 1 1 -2 2 TC 2TC T/2 T/2 4 4 2 25 ns ns ns ns ns ns ns ns (4, 13) (4) (13) (4) (13) (13) (4) (4) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 5 5 5 5 0 0 0 25 12.5 80 125 0.1% 62.5 62.5 6 6 MHz ns ns Min Max Units Notes (12) (13) (12) (12) ns ns ns ns ns ns TOH TOV (7, 11) (7) TOF TIS Datasheet 29 80960-40, -33, -25 Table 17. 80960CF AC Characteristics (40 MHz) (Sheet 2 of 2) Symbol Input Hold TIH1 TIH2 TIH3 TIH4 Parameter (1) D31:0 BOFF BTERM/READY HOLD Min 5 5 2 3 Max Units ns ns ns ns Notes TIH Relative Output Timings (2, 3, 4, 9) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST,DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High DT/R Valid to DEN Falling N*T - 6 T-4 T-6 T-4 T-6 6 N*T + 6 T+4 T+6 T+4 T+6 ns ns ns ns ns ns ns ns ns ns (5) (5) (6) (7) N*T 4 (N+1)*T-8 T/2 - 7 T/2 - 4 (N+1)*T+6 Relative Input Timings (2, 3, 4) TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) 6 5 12 7 7 3 3 T/4 + 1 ns ns ns ns ns ns ns ns (14) (14) (8) (8) (16) (16) (15) (15) NOTES: 1. 80960CF-40 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test Conditions. 2. See Table 19 for all notes related to AC specifications. 30 Datasheet 80960-40, -33, -25 Table 18. 80960CF AC Characteristics (33 MHz) (Sheet 1 of 2) Symbol Parameter (1) Input Clock (2, 10) TF TC TCS TCH TCL TCR TCF CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time Output Clocks (2, 9) TCP T TPH TPL TPR TPF CLKIN to PCLK2:1 Delay PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time PCLK2:1 Fall Time Min Max Units Notes 0 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 5 5 5 5 0 0 30 15 66.66 125 0.1% 62.5 62.5 6 6 MHz ns ns (12) (13) (12) (12) ns ns ns ns ns ns In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) -2 2 TC 2TC (T/2) - 2 (T/2) - 2 1 1 2 25 ns ns ns ns (4,13) (4) (13) (4) (13) (13) (4) (4) T/2 T/2 4 4 ns ns ns ns Synchronous Outputs (9) Output Valid Delay, Output Hold A31:2 TOH1, TOV1 BE3:0 TOH2, TOV2 TOH3, TOV3 ADS TOH4, TOV4 W/R TOH5, TOV5 D/C, SUP, DMA TOH6, TOV6 BLAST, WAIT TOH7, TOV7 DEN TOH8, TOV8 HOLDA, BREQ LOCK TOH9, TOV9 TOH10, TOV10 DACK3:0 TOH11, TOV11 D31:0 DT/R TOH12, TOV12 TOH13, TOV13 FAIL TOH14, TOV14 EOP3:0/TC3:0 Output Float for all outputs Synchronous Inputs (2, 10, 11) Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD D31:0 BOFF BTERM/READY HOLD 3 17 7 7 5 5 2 3 ns ns ns ns ns ns ns ns (7, 11) 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 14 16 18 18 16 16 16 16 16 18 16 T/2 + 14 14 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TOH TOV (7, 11) (7) TOF TIS TIH Datasheet 31 80960-40, -33, -25 Table 18. 80960CF AC Characteristics (33 MHz) (Sheet 2 of 2) Symbol Parameter (1) Min Max Units Notes Relative Output Timings (2, 3, 4, 9) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST,DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High DT/R Valid to DEN Falling N*T - 6 T-4 T-6 T-4 T-6 6 N*T + 6 T+4 T+6 T+4 T+6 ns ns ns ns ns ns ns ns ns ns (5) (5) (6) (7) N*T 4 (N+1)*T-8 T/2 - 7 T/2 - 4 (N+1)*T+6 Relative Input Timings (2, 3, 4) TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) 6 5 12 7 7 3 3 T/4 + 1 ns ns ns ns ns ns ns ns (14) (14) (8) (8) (16) (16) (15) (15) NOTES: 1. 80960CF-33 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test Conditions. 2. See Table 19 for all notes related to AC specifications. 32 Datasheet 80960-40, -33, -25 Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 1 of 3) Symbol Parameter (1) Input Clock (2, 10) TF TC TCS TCH TCL TCR TCF CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time Output Clocks (2, 9) TCP T TPH TPL TPR TPF CLKIN to PCLK2:1 Delay PCLK2:1 Period PCLK2:1 High Time PCLK2:1 Low Time PCLK2:1 Rise Time PCLK2:1 Fall Time Synchronous Outputs (9) Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 Output Float for all outputs Synchronous Inputs (2, 10, 11) TIS Min Max Unit Notes 0 In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 8 8 8 8 0 0 40 20 50 125 0.1% 62.5 62.5 6 6 MHz ns ns (12) (13) (12) (12) ns ns ns ns ns ns In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) -2 2 TC 2TC (T/2) - 3 (T/2) - 3 1 1 2 25 ns ns ns ns (4, 13) (4) (13) (4) (13) (13) (4) (4) T/2 T/2 4 4 ns ns ns ns (7, 11) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 16 18 20 20 18 18 18 18 18 20 18 T/2 + 16 16 20 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TOH TOV (7, 11) (7) TOF Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD D31:0 BOFF BTERM/READY HOLD 5 19 9 9 5 19 9 9 ns ns ns ns ns ns ns ns TIH Datasheet 33 80960-40, -33, -25 Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 2 of 3) Symbol Parameter (1) Min Max Unit Notes Relative Output Timings (2, 3, 4, 9) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High DT/R Valid to DEN Falling N*T - F T-4 T-6 T-4 T-6 6 N*T + 6 T+4 T+6 T+4 T+6 ns ns ns ns ns ns ns ns ns ns (5) (5) (6) (7) N*T 4 (N+1)*T- 8 T/2 - 7 T/2 - 4 (N+1)*T+6 Relative Input Timings (2, 3, 4) TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) DREQ3:0 Input Setup DREQ3:0 Input Hold XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) 8 7 14 9 9 5 3 T/4 + 1 ns ns ns ns ns ns ns ns (14) (14) (8) (8) (16) (16) (15) (15) 34 Datasheet 80960-40, -33, -25 Table 19. 80960CF AC Characteristics (25 MHz) (Sheet 3 of 3) Symbol Parameter (1) Min Max Unit Notes NOTES: 1. 80960CF-25 only, per the conditions in Section 4.2, Operating Conditions and Section 4.5.1, A.C. Test Conditions. 2. See Section 4.5.2, A.C. Timing Waveforms for waveforms and definitions. 3. See Figure 16 for capacitive derating information for output delays and hold times. 4. See Figure 17 for capacitive derating information for rise and fall times. 5. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 6. N = Number of wait states inserted with READY. 7. Output Data and/or DT/R may be driven indefinitely following a cycle when there is no subsequent bus activity. 8. Since asynchronous inputs are synchronized internally by the 80960CF, they have no required setup or hold times to be recognized and for proper operation. However, to ensure recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 9. These specifications are ensured by the processor. 10.These specifications must be met by the system for proper operation of the processor. 11. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 12.In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 13.When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than 0.1% between adjacent cycles. 14.In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 23.) 15.In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to ensure the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 24.) 16.The interrupt pins are synchronized internally by the 80960CF. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To ensure recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 4.5.1 A.C. Test Conditions The AC Specifications in Section 4.5, "A.C. Specifications" on page 29 are tested with the 50 pF load shown in Figure 7. Figure 16 shows how timings vary with load capacitance. Specifications are measured at the 1.5 V crossing point, unless otherwise indicated. Input waveforms are assumed to have a rise and fall time of < 2 ns from 0.8 V to 2.0 V. See Section 4.5.2, "A.C. Timing Waveforms" on page 36 for AC specification definitions, test points and illustrations. Figure 7. A.C. Test Load Output Pin CL CL = 50 pF for all signals F_CX008A Datasheet 35 80960-40, -33, -25 4.5.2 A.C. Timing Waveforms Figure 8. Input and Output Clocks Waveform CLKIN 1.5 V TCP T PCLK2:1 1.5 V TPH TPR TPL TPF 2.4 V 1.5 V 0.45 V F_CX009A Figure 9. CLKIN Waveform TCR TCF 2.0 V 1.5 V 0.8 V TCH TCL TC F_CX010A 36 Datasheet 80960-40, -33, -25 Figure 10. Output Delay and Float Waveform PCLK2:1 1.5 V 1.5 V TOH Outputs 1.5 V TOV Min Max 1.5 V TOF Outputs 1.5 V Min Max 1.5 V F_CX011A NOTES: 1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum output delay is referred to as Output Hold (TOH). 2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes less that ILO in magnitude. Figure 11. Input Setup and Hold Waveform PCLK2:1 1.5 V 1.5 V TIH Max Valid 1.5 V TIS Min Inputs: (READY, HOLD, BTERM, BOFF, DREQ3:0, D31:0 on reads) F_CX012A NOTE: TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. Datasheet 37 80960-40, -33, -25 Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform PCLK2:1 1.5 V 1.5 V 1.5 V Min NMI, XINT7:0 1.5 V TIS TIH Min Valid 1.5 V F_CX013A Figure 13. Hold Acknowledge Timings PCLK2:1 1.5 V 1.5 V TOF Min Max 1.5 V TOV Min Max Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA TIH Min HOLD 1.5 V Valid 1.5 V Valid TIS Min TIH Min TIS Min 1.5 V 1.5 V TOV Min Max HOLDA 1.5 V TOV Min 1.5 V Max 1.5 V F_CX014A NOTES: 1. TOV TOH - OUTPUT DELAY - Maximum output delay is referred to as Output Valid Delay (TOV); minimum output delay is referred to as Output Hold (TOH). 2. TOF - OUTPUT FLOAT DELAY - Output float condition occurs when the maximum output current becomes less that ILO in magnitude. 3. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 38 Datasheet 80960-40, -33, -25 Figure 14. Bus Backoff (BOFF) Timings PCLK2:1 1.5 V 1.5 V TOF Min 1.5 V TOV Max Min 1.5 V 1.5 V Valid Max Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA TIH Valid 1.5 V TIS TIH TIS BOFF 1.5 V 1.5 V 1.5 V F_CX015A Figure 15. Relative Timings Waveforms PCLK2:1 1.5 V 1.5 V 1.5 V 1.5 V ADS 1.5 V TAVSH 1.5 V A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA D31:0 1.5 V 1.5 V TNLQV TDVNH Out 1.5 V TNHQX 1.5 V WAIT 1.5 V TAVEL TNLNH DT/R TEHTV DEN D31:0 1.5 V 1.5 V TVEL 1.5 V In VIH VIL F_CX016A Datasheet 39 80960-40, -33, -25 4.5.3 Derating Curves Figure 16. Output Delay or Hold vs. Load Capacitance Output Valid Delays (ns) @ 1.5 V nom + 10 nom + 5 All outputs except: LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL nom 50 100 CL (pF) 150 Note: PCLK Load = 50pF F_CX017A Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 10 8 Time (ns) 0.8 V to 2.0 V 10 8 Time (ns) 0.8 V to 2.0 V 6 4 2 6 4 2 CL (pF) 50 100 150 CL (pF) 50 100 150 a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ DACK3:0, EOP3:0/TC3:0, FAIL b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL F_CX019A Figure 18. ICC vs. Frequency and Temperature--80960CF-33 and -25 900 TC = 100 C ICC (mA) TC = 0 C 0 0 ICC - ICC under test conditions fPCLK (MHz) 33 F_CX020A 40 Datasheet 80960-40, -33, -25 Figure 19. ICC vs. Frequency and Temperature--80960CF-40 1100 TC = 1000 ICC (mA) TC = 85 C ICC - ICC under test conditions 0 0 fPCLK (MHz) 40 F_CX020A 5.0 Reset, Backoff and Hold Acknowledge Table 20 lists the condition of each processor output pin while RESET is asserted (low). Table 21 lists the condition of each processor output pin while HOLDA is asserted (high). In Table 21, with regard to bus output pin state only, the Hold Acknowledge state takes precedence over the reset state. Although asserting the RESET pin internally resets the processor, the processor's bus output pins do not enter the reset state when Hold Acknowledge has been granted to a previous HOLD request (HOLDA is active). Furthermore, the processor grants new HOLD requests and enters the Hold Acknowledge state even while in reset. For example, when HOLD is asserted while HOLDA is inactive and the processor is in the reset state, the processor's bus pins enter the Hold Acknowledge state and HOLDA is granted. The processor is not able to perform memory accesses until the HOLD request is removed, even when the RESET pin is brought high. This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus. Datasheet 41 80960-40, -33, -25 Table 20. Reset Conditions Pins A31:2 D31:0 BE3:0 W/R ADS WAIT BLAST DT/R DEN LOCK BREQ D/C DMA SUP FAIL DACK3:0 EOP3:0/TC3:0 State During Reset (HOLDA inactive) Floating Floating Driven high (Inactive) Driven low (Read) Driven high (Inactive) Driven high (Inactive) Driven low (Active) Driven low (Receive) Driven high (Inactive) Driven high (Inactive) Driven low (Inactive) Floating Floating Floating Driven low (Active) Driven high (Inactive) Floating (Set to input mode) Table 21. Hold Acknowledge and Backoff Conditions Pins A31:2 D31:0 BE3:0 W/R ADS WAIT BLAST DT/R DEN LOCK BREQ D/C DMA SUP FAIL DACK3:0 EOP3:0/TC3:0 Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Driven (High or low) Floating Floating Floating Driven high (Inactive) Driven high (Inactive) Driven (When output) State During HOLDA 42 Datasheet 6.0 CLKIN VCC - ONCE VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. Figure 20. Cold Reset Waveform Bus Waveforms ADS, LOCK, WAIT, DEN, DACK3:0 BLAST Tdelay 1 PCLK INST, SUP, DMA, A31:2, D/C, BE3:0 D31:0, EOP/TC3:0 Inputs RESET CLKIN and VCC Stable to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN periods in 1x Mode. RESET high to First Bus activity, approximately 32 PCLK periods. F_CX021A Tsetup 1PCLK Thold 1 PCLK Valid STEST Invalid W/R, DT/R, BREQ, FAIL PCLK2:1 Datasheet 80960-40, -33, -25 43 ADS, LOCK, WAIT, DEN, DACK3:0 W/R, DT/R, BREQ, FAIL BLAST SUP, DMA, A31:2, D/C, BE3:0 D31:0, EOP/TC3:0 STEST Maximum RESET Low to RESET State 4 PCLK Periods RESET Valid Tsetup 1 PCLK Thold 1 PCLK RESET High to First Bus Activity, Approximately 32 PCLK Periods Minimum RESET Low Time 16 PCLK Periods Tdelay 1PCLK 44 Figure 21. Warm Reset Waveform PCLK2:1 80960-40, -33, -25 Datasheet F_CX022A ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLD, HOLDA, BLAST, FAIL, SUP,BREQ, DMA, EOP3:0/TC3:0, STEST, XINT7:0, NMI, DACK3:0, DREQ3:0 READY, BTERM PCLK2:1 VCC VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. CLKIN and VCC Stable and RESET low and ONCE low to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN Periods in 1x Mode. ONCE RESET CLKIN Datasheet CLKIN may not float. It must be driven high or low or continue to run Maximum 32 CLKIN Periods Required after ONCE Mode entered F_CX023A Figure 22. Entering the ONCE State 80960-40, -33, -25 45 80960-40, -33, -25 Figure 23. Clock Synchronization in the 2-x Clock Mode CLKIN 1.5 V 1.5 V 1.5 V 1.5 V TIH TIS RESET 1.5 V 1.5 V PCLK2:1 (Case 1) Max Min PCLK2:1 (Case 2) 1.5 V TCP 1.5 V Max Min Min TCP Max 1.5 V TCP 1.5 V 1.5 V SYNC 1.5 V Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 F_CX024A Figure 24. Clock Synchronization in the 1-x Clock Mode 2x CLK CLKIN 1.5 V 1.5 V TIH TIS RESET 1.5 V Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN. The RESET pin is sampled when PCLK is high. F_CX025A 46 Datasheet 80960-40, -33, -25 Figure 25. Non-Burst, Non-Pipelined Requests Without Wait States reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 0 00000 NXDA 11-10 0 00 NRDD 9-8 X xx NRAD 7-3 0 00000 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A PCLK D A D A D ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid Valid WAIT D31:0 In Out In F_CX026A Datasheet 47 80960-40, -33, -25 Figure 26. Non-Burst, Non-Pipelined Read Request With Wait States reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 3 00011 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A 3 2 1 D 1 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK Valid WAIT D31:0 In F_CX027A 48 Datasheet 80960-40, -33, -25 Figure 27. Non-Burst, Non-Pipelined Write Request With Wait States reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 3 00011 NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 X xxxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Disabled 0 0 A 3 2 1 D 1 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK Valid WAIT D31:0 Out F_CX028A Datasheet 49 80960-40, -33, -25 Figure 28. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-Bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 0 00 NRDD 9-8 0 00 NRAD 7-3 0 00000 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A PCLK D D D D A ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX029A 50 Datasheet 80960-40, -33, -25 Figure 29. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX030A Datasheet 51 80960-40, -33, -25 Figure 30. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 0 00 NWAD 16-12 0 00000 NXDA 11-10 0 00 NRDD 9-8 X xx NRAD 7-3 X xxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A PCLK D D D D A ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 Out0 Out1 Out2 Out3 F_CX031A 52 Datasheet 80960-40, -33, -25 Figure 31. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 1 01 NWAD 16-12 2 00010 NXDA 11-10 1 01 NRDD 9-8 X xx NRAD 7-3 X xxxxx PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 Out0 Out1 Out2 Out3 F_CX032A Datasheet 53 80960-40, -33, -25 Figure 32. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 16-bit 01 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R Valid BLAST DT/R DEN A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 BE1/A1 WAIT D31:0 D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 F_CX033A 54 Datasheet 80960-40, -33, -25 Figure 33. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 8-bit 00 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 1 01 NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 OFF 0 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 D 1 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4 Valid W/R BLAST DT/R DEN A3:2 A3:2 = 00, 01, 10 or 11 BE1/A1, BE0/A0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 WAIT D31:0 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 F_CX034A Datasheet 55 80960-40, -33, -25 Figure 34. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 X xx NRAD 7-3 0 00000 PipeLining 2 ON 1 External Ready Control 1 X x Burst 0 Disabled 0 31-23 0 0..0 21 0 0 A A' D A'' D' A''' D'' A'''' D''' D'''' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Valid Valid Valid Invalid W/R Invalid A3:2 BE3:0 Valid Valid Valid Valid Valid Invalid D31:0 IN D IN D' IN D'' IN D''' IN D'''' WAIT BLAST DT/R DEN Non-pipelined request concludes pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. F_CX035A 56 Datasheet 80960-40, -33, -25 Figure 35. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 X xx NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 X xx NRAD 7-3 1 00001 PipeLining 2 ON 1 External Ready Control 1 X x Burst 0 Disabled 1 31-23 0 0..0 21 0 0 A 1 A' D 1 D' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Invalid W/R Invalid A3:2 BE3:0 Valid Valid Invalid D31:0 IN D IN D' WAIT BLAST DT/R DEN Non-pipelined request concludes pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. F_CX036A Datasheet 57 80960-40, -33, -25 Figure 36. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 0 00 NRAD 7-3 0 00000 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A D D D A' D D' D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid InValid W/R InValid A3:2 00 01 10 11 Valid Valid InValid D31:0 IN D IN D IN D IN D IN D IN D WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin Pipelined reads conclude, non-pipelined requests begin F_CX037A 58 Datasheet 80960-40, -33, -25 Figure 37. Burst, Pipelined Read Request With Wait States, 32-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 32-bit 10 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Invalid W/R Invalid A3:2 00 01 10 11 Valid Invalid D31:0 IN D IN D IN D IN D IN D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. F_CX038A Datasheet 59 80960-40, -33, -25 Figure 38. Burst, Pipelined Read Request With Wait States, 16-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 16-bit 01 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK W/R Valid Valid Invalid Invalid A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 Valid Invalid BE1/A1 Valid Invalid D31:0 D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 D15:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. F_CX040A 60 Datasheet 80960-40, -33, -25 Figure 39. Burst, Pipelined Read Request With Wait States, 8-Bit Bus reserved reserved Function Bit Value Byte Order 22 X x Bus Width 20-19 8-bit 00 NWDD 18-17 X xx NWAD 16-12 X xxxxx NXDA 11-10 X xx NRDD 9-8 1 01 NRAD 7-3 2 00010 PipeLining 2 ON 1 External Ready Control 1 Burst 0 31-23 0 0..0 21 0 0 Disabled Enabled 1 0 A 2 1 D 1 D 1 D 1 A' D 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, LOCK W/R Valid Valid Invalid Invalid Invalid A3:2 A3:2 = 00, 01, 10, or 11 Valid BE1/A1, BE0/A0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11 Valid Invalid D31:0 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 D7:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, non-pipelined requests begin. F_CX039A Datasheet 61 80960-40, -33, -25 Figure 40. Using External READY Quad-Word Read Request NRAD = 0, NRDD = 0, NXDA = 0 Ready Enabled Quad-Word Write Request NWAD = 1, NWDD = 0, NWDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R Valid Valid BLAST DT/R DEN READY BTERM A3:2 00 01 10 11 00 01 10 11 WAIT D31:0 D0 D1 D2 D3 D0 D1 D2 D3 F_CX041A 62 Datasheet 80960-40, -33, -25 Figure 41. Terminating a Burst with BTERM Quad-Word Write Request NWAD = 0, NWDD = 0, NWDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN READY See Note BTERM A3:2 00 01 10 11 WAIT D31:0 D0 D1 D2 D3 Note: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal may terminate a bus access when the signal is asserted during the last (or only) data transfer of the bus access. F_CX042A Datasheet 63 80960-40, -33, -25 Figure 42. BOFF Functional Timing Regenerate ADS ADS BURST BURST MAY CHANGE BLAST NON-BURST READY BOFF SUSPEND REQUEST A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) Begin Request BOFF may be asserted to suspend request BOFF may not be asserted Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0 End Request BOFF may not be asserted F_CX043A 64 RESUME REQUEST Datasheet 80960-40, -33, -25 Figure 43. HOLD Functional Timing Word Read Request NRAD=0, NXDA=0 Word Read Request NRAD=1, NXDA=1 Hold State Hold State PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R Valid Valid BLAST HOLD HOLDA F_CX044A Datasheet 65 80960-40, -33, -25 Figure 44. DREQ and DACK Functional Timing PCLK2:1 System Clock ADS ! (BLAST & READY & !WAIT) DACKx (All Modes) DREQx (Case 1) Start DMA Bus Request End DMA Bus Request (see Note) DMA Acknowledge high to prevent next bus cycle tIS6 tIH6 DMA Request high to prevent next bus cycle tIS6 tIH6 DREQx (Case 2) Note: 1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized packing modes and destination synchronized unpacking modes. 2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. This applies to all other DMA transfers. F_CX018A 3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined by ADS and BLAST). Figure 45. EOP Functional Timing EOP 2 CLKs Min 15 CLKs Max Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge triggered. EOP must be for a minimum of 2 clock cycles then deasserted within 15 clock cycles. held F_CX045A 66 PCLK2:1 Datasheet 80960-40, -33, -25 Figure 46. Terminal Count Functional Timing PCLK2:1 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. When the last LOAD/STORE bus request is executed as multiple bus accesses, the TC may be active for the entire bus request. Refer to the i960(R) Cx Microprocessor User's Manual for further information. F_CX046A Figure 47. FAIL Functional Timing RESET (Internal Self-Test) Pass (Bus Test) Pass ~65,000 Cycles Fail 5 Cycles FAIL Fail F_CX047A 102 Cycles Datasheet 67 80960-40, -33, -25 Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions Byte Offset 0 4 8 12 16 20 24 Word Offset 0 1 2 3 4 5 6 Short Request (Aligned) Byte, Byte Requests Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Byte, Short, Byte, Requests Word Load/Store Short, Short Requests Byte, Short, Byte Requests One Double-Word Burst (Aligned) Byte, Short, Word, Byte Requests Short, Word, Short Requests Double-Word Load/Store Byte, Word, Short, Byte Requests Word, Word Requests One Double-Word Request (Aligned) F_CX048A 68 Datasheet 80960-40, -33, -25 Figure 49. A Summary of Aligned and Unaligned Transfers for Little Endian Regions 0 Byte Offset 0 1 2 3 4 One Three-Word Request (Aligned) Byte, Short, Word, Word, Byte Requests Triple-Word Load/Store Short, Word, Word, Short Requests Byte, Word, Word, Short, Byte Requests Word, Word, Word Requests Word, Word, Word Requests Word, Word, Word Requests 5 6 4 8 12 16 20 24 Word Offset One Four-Word Request (Aligned) Byte, Short, Word, Word, Word, Byte Requests Quad-Word Load/Store Short, Word, Word, Word, Short Requests Byte, Word, Word, Word, Short, Byte Requests Word, Word, Word, Word Requests DoubleWord, DoubleWord, Requests F_CX049A Datasheet 69 80960-40, -33, -25 Figure 50. Idle Bus Operation Write Request NWAD=2, NXDA = 0 Ready Disabled Idle Bus (not in Hold Acknowledge state) Read Request NWAD=2, NXDA = 0 Ready Disabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0 LOCK Valid Valid Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid WAIT D31:0 Out In READY, BTERM F_CX050A 70 Datasheet |
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